module dff(clk,clr,rst,d,q);//clr清0，rst复位
	input clk,clr,rst,d;
	output q;
	reg q;
	always@(posedge clk or posedge clr)
	begin
		if(clr==1'b1)q<=1'b0;
		else if(rst==1'b1)q<=1'b1;
		else q<=d;
	end
endmodule